Chapter 7 Hardware Implementation Tools
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The testing and embedding speech processing algorithm on general purpose PC and
dedicated DSP platform require specific hardware implementation tools. Real time digital signal
processing made considerable advancements after the introduction of specialized DSP
processors. Suitable starter kits with a specific DSP processor and related software tools such as
compilers, assemblers, simulators, debuggers, and so on, are provided in order to make system
design and application development easier. The 32-bit floating point processor TMS320C6713
from Texas Instruments is very powerful for real time speech and audio processing algorithm
implementations. This DSP processor is based on the VLIW (Very Large Instruction Word)
technology, which allows fast parallel computing jointly using its optimized "C" compiler. For a
rapid evaluation of the TMS320C6713 processor a Developer Starter Kit 6713 (DSK 6713) is
available from Spectrum Digital Incorporation; comprises a board and the software tools. The
board must be connected to a standard PC running under its integrated development
environment- Code Composer Studio (CCS IDE). For rapid prototyping, testing and debugging
of developed algorithm the Real Time Workshop (RTW) toolbox and MATLAB link for
embedded target called Target Support Package TC6 is used.
7.1 The Digital Signal Processor: TMS320C6713
The TMS320C6000 platform of digital signal processors (DSPs) is part of the TMS320
family of DSPs. The TMS320C67x (‟C67x) devices are floating-point DSPs in the
TMS320C6000 platform. The TMS320C67x DSPs (including the TMS320C6713 device)
compose the floating-point DSP generation in the TMS320C6000 DSP platform [1]. The C6713
device is based on the high-performance, advanced very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making this DSP an excellent choice for
multichannel and multifunction applications. Operating at 225 MHz, the C6713 delivers up to
1350 million floating-point operations per second (MFLOPS), 1800 million instructions per
second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-
accumulate operations per second (MMACS). Operating at 300 MHz, the C6713 delivers up to
1800 million floating-point operations per second (MFLOPS), 2400 million instructions per
second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-
accumulate operations per second (MMACS).
The C6713 uses a two-level cache-based architecture and has a powerful and diverse set
of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the
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