MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Instrukcja Użytkownika Pobierz pdf (Strona 32)

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DSP Selection Guide 31

ADSP-2100 Architecture

Providing over 15 Years of Code-Compatible DSP Excellence

Special Instructions

The ADSP-2100 architecture contains dedicated

loop hardware and a “DO UNTIL” loop instruc-

tion that supports loops ranging from zero to 16K

iterations, or loops with infinite iterations. The

ADSP-218x supports up to four-deep nesting via

its loop hardware and the ADSP-219x supports

as many as eight. In addition to the standard

arithmetic and logic instructions, the ALU (arith-

metic-logic unit) supports division primitives.

The ADSP-219x program sequencer features a

6-deep pipeline, and supports delayed branching.

The ADSP-219x buses and instruction cache

also provide rapid, unimpeded data flow to the

core to maintain the high execution rate.

Compiler Friendly

Many of the enhancements to the ADSP-219x

architecture were made to improve compiler

efficiency. More flexible DAG addressing

modes, added secondary DAG register,

increased depth to stacks, and extended address

reach to 16M words drastically improves com-

piler code efficiency.

Code Compatible

High Performance

Low Cost

ADSP-2186

80 MIPS

ADSP-2185

80 MIPS

ADSP-218x

80 MIPS

ADSP-2196

160 MIPS

ADSP-2195

160 MIPS

ADSP-2191

160 MIPS

ADSP-219x

300 MIPS

ADSP-219x

ADSP-218x

Performance Upgrade

Low Power

Low Cost

ADSP-218x

Platform

ADSP-219x

Platform

Roadmap

Higher Performance

Processor

Core

Time

Performance

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 61 62

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