MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Instrukcja Użytkownika Pobierz pdf (Strona 9)

ADI DSP Key Benefits

8 DSP Selection Guide

http://www.analog.com/dsp

language support. To understand the benefits of

ADI’s families of 16- and 32-bit DSPs and how

ADI’s architectures are optimized for digital sig-

nal processing, keep in mind three basic features

of DSP. DSPs must have the ability to:

1) Perform fast arithmetic

2) Fetch data at a fast rate

3) Sequence efficiently through repetitive

operations

Selecting a DSP processor can be a difficult task.

Design engineers are concerned with time-to-mar-

ket, for which ease of use, quality development

tools, extensive application engineering support,

and the availability of algorithm code are critical.

Of course, designers are also concerned with low

production cost, low power consumption, system

integration, and other criteria such as clock fre-

quency, size of on-chip memory, and high-level

• One cycle per instruction execution

• ADSP-218x requires no extra latency cycles for decision branches, condition

code checking, or subroutine calls

• Delayed branches increase efficiency on pipelined architectures such as the

SHARC

and ADSP-219x DSP families

• Deterministic operations make it easy to develop, profile, and benchmark code

• Blackfin



DSP allows for 1 instruction and 2 data fetches per cycle

• All ADSP-21xx Family members share the same base architecture and

assembly language

• All SHARC DSP Family members share the same base architecture and

assembly language

• No need to learn or invest in new development tools when moving from one

family member to another

• Software investment is preserved

• Blackfin DSPs utilize an interlocked pipeline so future core versions will pro-

tect SW code investment

• Algebraic syntax assembly language makes code easy to use, easy to

learn, and easy to read

• Unlike competitors who use mnemonics like SPAC and XORX, ADI

assembly language syntax makes programming in highly-efficient assem-

bly language easy

• Fast core processing, large on-chip memories, and high bandwidth I/O

simplify real-time system development

• Up to 14 channels of non-intrusive Direct Memory Access (DMA) allow

data movement without interrupting math processing

• Blackfin DSPs offer dual-ported L1 memory so the core can be fed while

simultaneously loading in new data non-intrusively

• Provides ample on-chip storage for most common DSP tasks such as digi-

tal filtering and FFTs, eliminating the need for off-chip memory

• Minimizes off-chip memory access wait states

• On-chip hardware manages looping and provides the most efficient code

execution with no extra programming for repetitive DSP code

• No need to control looping with complex software

• Increase speed or memory integration within a common pin-out

• Adds flexibility without requiring board redesign

Single Cycle Instruction

Execution

Code Compatible Family

Members

Simple Programming

Language

Balanced Core, Memory

and I/O Integration

Large On-Chip Memory

Efficient Program

Sequencing and

Zero-Overhead Looping

Pin-for-Pin Compatible

Family Members

BenefitKey Feature

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