MATLAB SIMULINK HDL CODER 1 Instrukcja Użytkownika

9/21/20111Implementing MATLAB and SimulinkAlgorithmsgon FPGAsStefano OlivieriMarco Visintini1© 2011 The MathWorks, Inc.Stefano OlivieriSenior Applicat

9/21/201110MATLABMATLAB® ® andand SimulinkSimulink®®Algorithm and System DesignAlgorithm and System DesignModel Refinement for HardwareModel Refinemen

9/21/201111Model-Based Design for ImplementationVerificationMATLABMATLAB® ® andand SimulinkSimulink®®Algorithm and System DesignAlgorithm and System D

9/21/201112MATLABMATLAB® ® andand SimulinkSimulink®®Algorithm and System DesignAlgorithm and System DesignModel Refinement for HardwareModel Refinemen

9/21/201113ChallengeSemtech Speeds Development of Digital Receiver FPGAs and ASICsgAccelerate the development of optimized digital receiver chains for

9/21/201114 Corner detection is used in many Image Processing applicationsHarris-Stephens’ Corner Detection– Image mosaicking– Tracking – Object reco

9/21/201115From Algorithm to Synthesizable RTLMATLABMATLAB® ® andand SimulinkSimulink®®Algorithm and System DesignAlgorithm and System DesignModel Ref

9/21/201116Fixed Point AnalysisCorner Detection Convert floating point to optimized fixed point models–Automatic tracking of signal range (also inter

9/21/201117Simulink Library Support for HDLHDL Supported Blocks 170 blocks supported Core Simulink Blocks– Basic and Array Arithmetic, Look-Up Table

9/21/201118Integrating Legacy HDL CodeHDL Supported BlocksIntegrate legacy HDL code in Simulink using black boxes40Configure the interface to legacy H

9/21/201119Break42 Use Model-Based Design to provide an integrated workflowThings to remember ….DESIGN Speed up algorithm development with a unified

9/21/20112Introducing The SpeakersXilinx:Daniele BagniDaniele BagniDSP Specialist EMEAMathWorks: Stefano OlvieriSenior Application Engineer3Signal

9/21/201120Wh t ld lik t tWhat would you like to get from automatic code generation?44generation?DESIGNHardware Design Challenges:Optimizing for Speed

9/21/201121IIR Low Pass FilterDirect-Form II Transposed SOS46From Algorithm to Optimized RTLMATLABMATLAB® ® andand SimulinkSimulink®®Algorithm and Sys

9/21/201122Hardware Design Challenges:Speed Optimization48Finding the critical path in your model can be challengingDemo: HDL Workflow Advisor>>

9/21/201123Demo: HDL Workflow AdvisorPerform relevant checks for HDL code generation50Demo: HDL Workflow AdvisorSet options and generate automatically

9/21/201124Demo: HDL Workflow AdvisorCreate FPGA project Run P&R -and-Annotate timing information52Automated workflow from model to FPGA Analysi

9/21/201125Balancing pipeline registersSpeed Optimization critical pathparallel paths54 Multiple parallel paths through your model High risk to have

9/21/201126Distributed PipeliningSpeed Optimization 56 Distributed pipelining (model retiming) Automatic balancing of pipeline registers(focus on cr

9/21/201127Distributed PipeliningSpeed OptimizationMinimum period: 9.379ns MaximumFrequency:106 62MHzMaximum Frequency: 106.62MHz58Section 2Section 3D

9/21/201128IIR Low Pass FilterDirect-Form II Transposed SOS60Challenges: Data dependent resources to be shared Feedback loops Vectorized inputsDemo

9/21/201129Resource Sharing and StreamingArea Optimization Easy to explore different sharing optionsDirect feedback through resource utilization rep

9/21/20113MathWorks at a Glance Headquarters:NtikM h tt USNatick, Massachusetts US Other US Locations: California, Michigan, Texas, Washington DC E

9/21/201130 Steps To Reduce Power–Smaller/Efficient DesignsBetter Algorithm DesignPower Optimization Smaller/Efficient Designs– Reduce Clock Frequenc

9/21/201131Control Subsystem ExecutionPower OptimizationEnabled Subsystems Modules can be enabled and disabled66Triggered Subsystems Modules can be

9/21/201132 How do these techniques work with our Corner Detection algorithm??Harris-Stephens’ Corner DetectionDetection algorithm??68Summary: Corner

9/21/201133Summary: Code Generation Optimizations Shorter iteration cycles–Automatic HDL code generationAutomatic HDL code generation Flexible autom

9/21/201134 Use Model-Based Design to provide an integrated workflowThings to remember ….DESIGN Speed up algorithm development with a unified design

9/21/201135Verification Challenges:HDL VerificationDesign the Test Bench twiceDesign the Test Bench twice– 10 – to – 1 ratio of Test bench LOC – to

9/21/201136Digital Down Converter DDC acceptsp– A high sample-rate passband signal (may be 50 to 100 Msps) DDC produces– A low sample-rate baseband

9/21/201137What is the impact ofVerify Handwritten HDL Vector-Based Digital Down ConverterWhat is the impact of these differences?79Difficult to analy

9/21/201138Additional Methods for VerificationHDL Verification Techniques Co-simulation with MATLAB– Test Bench– Component Generate vector based tes

9/21/201139Ch llHarris Accelerates Verification of Signal Processing FPGAsChallengeStreamline a time-consuming manual process for testing signal proce

9/21/20114Key Industries Aerospace and Defense Automotive Biotech and Pharmaceutical Communications Education Electronics and Semiconductors En

9/21/201140Challenges:Testing algorithms on real hardware Motivation: building confidence But …… interfaces with peripherals 86pp& rest of the

9/21/201141FPGA-in-the-Loop verification Digital Down ConverterFlexible testbenchcreation in SimulinkRe-use system level test bench for FPGA verificat

9/21/201142From Algorithm to FPGA ImplementationMATLABMATLAB® ® andand SimulinkSimulink®®Algorithm and System DesignAlgorithm and System DesignModel R

9/21/201143Agenda9:45Welcome10:00Reduce FPGA Development Time with Model-Based Designpg11:00Break11:15Integrated HDL Verification12:00Xilinx Target-op

9/21/201144 Use Model-Based Design to provide an integrated workflowThings to remember ….DESIGN Speed up algorithm development with a unified design

9/21/201145How to adopt MathWorks technologies? MathWorks tools provide a technology to speed up pgyppdevelopment MathWorks services provide the sup

9/21/201146Were Your Expectations Met? Please complete and return seminar survey forms Your comments and feedback are very important to us991. Visit

9/21/20115Your Expectations Beyond the Agenda...11Corner Detection in Video Mosaicking(A Brief Example)13

9/21/20116 Use Model-Based Design to provide an integrated workflowThings to remember ….DESIGN Speed up algorithm development with a unified design

9/21/20117Memory Customized interfaces to peripheralsMemoryWe are going to focus onWhy do we use FPGAs?Analog I/ODigital I/OARMBridgeMemoryMemoryMemo

9/21/20118Where do you spend most of your time? Simulating designs? Creating designs and test benches?Algorithm DesignSystem Test BenchSystem Design

9/21/201191. Increase simulation speed 2. Simplify design entry, system test harness A Few Ways to Reduce Development Timecreation, and exploration3.