MATLAB SIMULINK HDL CODER 1 Instrukcja Użytkownika Pobierz pdf (Strona 44)

9/21/2011

 Use Model-Based Design to provide

an integrated workflow

Things to remember ….

DESIGN

 Speed up algorithm development

with a unified design environment

 Automate manual steps in

FPGA implementation to enable

shorter iteration c

cles

Algorithm

Development

MATLAB

Simulink

Stateflow

 Integrate FPGA development tools to

reduce verification time

 Shorter implementation time by 48% (total project 33%)

 Reduced FPGA prototype development schedule by 47%

ROI: Customer Adoption Of Model-Based Design

Time spent on FPGA/ASIC implementation

 Shorter design iteration cycle by 80%

FPGA Prototype 2

FPGA Prototype

1 2 ... 39 40 41 42 43 44 45 46

Brak uwag

MATLAB SIMULINK HDL CODER 1 Instrukcja Użytkownika Strona 44