MATLAB SIMULINK HDL CODER 1 Instrukcja Użytkownika Pobierz pdf (Strona 13)

9/21/2011

Challen

Semtech Speeds Development of

Digital Receiver FPGAs and ASICs

Accelerate the development of optimized digital

receiver chains for wireless RF devices

Solution

Use MathWorks tools for Model-Based Design to

generate production VHDL code for rapid FPGA

and ASIC implementation

Results

 Prototypes created 50% faster

“Writing VHDL is tedious, and the

handwritten code still needs to be

verified. With Simulink and Simulink

HDL Coder, once we have simulated

the model we can generate VHDL

The Semtech SX1231 wireless transceiver.

 Verification time reduced from weeks to days

 Optimized, better-performing design delivered

the

model

can

generate

VHDL

directly and prototype an FPGA. It

saves a lot of time, and the generated

code contains some optimizations we

hadn’t thought of.”

Frantz Prianon

Semtech

Link to user story

Case Study: Corner Detection Algorithm

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MATLAB SIMULINK HDL CODER 1 Instrukcja Użytkownika Strona 13