MATLAB SIMULINK HDL CODER 1 Instrukcja Użytkownika Pobierz pdf (Strona 41)

9/21/2011

41

FPGA-in-the-Loop verification

Digital Down Converter

Flexible testbench

creation in Simulink

Re-use system level test

bench for FPGA

verification

88

Building confidence that

the design works on real

hardware

Summary: Verification

 Integration of FPGA development tools enhances

verification

verification

– Improved analysis, flexible testbench creation

(multi domain, feedback loops)

– Integration with HDL verification

– Integration with FPGA verification

A tomation gi es shorter iteration c cles

89



A

u

tomation

gi

v

es

shorter

iteration

c

y

cles

– Automatically generated verification models for:

 HDL Co-Simulation

 FPGA-in-the-Loop

– Wizards for legacy HDL code

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